The present invention relates generally to programming of a memory and more particularly to a system and method for reliably programming such a memory.
When testing memory cells in a memory array such as an EEPROM array, there are three different time periods that tests are performed to determine whether the bit cells are being read properly. The first time period is when the array is in the fabrication or manufacturing area. The second time period is when the array is in a product, as part of a circuit. The third time period is when the circuit is part of an overall system, as in a sensor.
In the fabrication time period, typically the functionality of the device is tested via a test pattern on the scribe. In this time period, the circuit is tested is tested on a test die. Typically a go/no-go test is utilized, that is, it is determined if a bit cell is being read properly when the test voltage is above a first threshold voltage and when the test voltage is below a second threshold voltage. In addition, only specified areas of the test die are tested and therefore there may be some areas on the die that cannot be read.
During the second time period when the array is part of the circuit, selected bits in the EEPROM are tested typically for data retention. This is typically also a go or no-go test. This test is not performed on a bit by bit basis.
Finally, in the third time period when the circuit is part of a device or system, the device is programmed according to data sheet specification, and there may be a sample quality test to determine if there is data retention. There is typically no test to ensure correct voltage and there is no test for any marginal bit performance within a device. Typically, there is a high cost if there is a failure and so the way failure mode is addressed is through additional redundancy in the memory to minimize the failure mode. During all of the above time periods defective arrays may occur because some of the bit cells can not be properly read.
Accordingly, what is desired is that in the circuit and sensor test and calibration environment, each bit can be tested for threshold voltage. Also, it is important to reduce the overall time required to test the device. Finally, it is important to reduce the amount of redundancy, thereby saving silicon area. The present invention addresses such a need.
A method for testing a cell in a device for reliability is disclosed. The cell us coupled to a reference voltage and a current source. The method and system comprises measuring a mirrored current through the device at first predetermined gate voltage and measuring a mirrored current through the device at a second predetermined voltage. The method and system includes determining the threshold voltage of the cell and heating the device for a predetermined period of time. Finally, the method and system includes calculating a new threshold voltage if the measured mirrored current is different from the previously measured current.
Accordingly, a system and method in accordance with the present invention addresses this drift problem by testing the characteristics of the memory array on a bit by bit basis. A system and method in accordance with the present invention includes a mirrored current source arrangement. The mirrored current source arrangement allows for the determination of the overall change in characteristic of the threshold voltage. In so doing, the device can be tested more accurately and quickly, thereby reducing the time for testing and increasing the reliability of the device.